Exemplary embodiments of the present invention relate to an impedance adjusting device which matches impedance of input/output pads for communication with external circuits by compensating for an increase in output impedance caused by power supply impedance in a semiconductor device.
A variety of semiconductor devices are implemented with integrated circuit chips, such as CPUs, memories, and gate arrays. Such semiconductor devices are incorporated into a variety of electrical products, such as personal computers, servers, and workstations. In most cases, semiconductor devices include reception circuits configured to receive a variety of external signals through input pads from external circuits, and output circuits configured to provide a variety of internal signals through output pads to external circuits.
Meanwhile, as the operating speeds of electrical products increase, swing widths of signals transmitted between semiconductor devices are gradually reduced in order to minimize delay time necessary for signal transfer. However, as the swing widths of the signals are reduced, the effects of external noises on the signals are increased, and therefore, signal reflection at interface terminals (i.e., input/output terminals) due to impedance mismatching becomes more severe. The impedance mismatching is generally caused by external noises or variations in power supply voltage, operating temperature, or fabrication process. The impedance mismatching may make it difficult to accurately transfer data at high speed and may distort output data outputted from data output terminals of the semiconductor device. Therefore, where the reception circuit of the semiconductor device receives the distorted output signals through the input terminals, setup/hold operations may fail or incorrect determinations of input levels may occur frequently.
In order to address the above concerns, semiconductor devices requiring high-speed operations have adopted impedance matching circuits, called on-die termination (ODT) devices, located in the vicinity of pads inside integrated circuit chips. In a typical ODT scheme, a source termination is performed at a transmission side by an output circuit, and a parallel termination is performed at a reception side by a termination circuit coupled in parallel to the reception circuit which is coupled to an input pad.
A ZQ calibration refers to a procedure of generating impedance codes which change according to variations of process, voltage, and temperature (PVT) conditions. A termination impedance value is adjusted using impedance codes generated from the ZQ calibration. Generally, a pad to which an external resistor, serving as a calibration reference impedance, is coupled is referred to as a ZQ pad. For this reason, the term “ZQ calibration” is widely used.
FIG. 1 is a block diagram of a conventional calibration circuit.
Referring to FIG. 1, the conventional calibration circuit includes a pull-up reference impedance unit 110, a dummy reference impedance unit 120, a pull-down reference impedance unit 130, comparison units 102 and 103, and counter units 104 and 105.
Upon operation of the conventional calibration circuit, the comparison unit 102 compares a reference voltage (generally, VDDQ/2) with a voltage of a first calibration node ZQ, which is the result of a voltage division between an external resistor 101 (hereinafter, assumed to be 240Ω) coupled to a ZQ pad and the pull-up reference impedance unit 110. The comparison unit 102 generates an up/down signal UP/DN as a result of the comparison.
The counter unit 104 generates a pull-up impedance code PCODE<0:N> in response to the up/down signal UP/DN outputted from the comparison unit 102. The pull-up impedance code PCODE<0:N> adjusts the impedance value of the pull-up reference impedance unit 110 by turning on/off parallel resistors inside the pull-up reference impedance unit 110 (the resistance values of the parallel resistors are designed according to binary weights). The adjusted impedance value of the pull-up reference impedance unit 110 again influences the voltage of the first calibration node ZQ, and the above-described operations are repeated. As a result, the calibration operation is repeated until the impedance value of the pull-up reference impedance unit 110 becomes equal to the impedance value of the external resistor 101. This operation is referred to as a pull-up calibration operation.
The pull-up impedance code PCODE<0:N> generated by the above-described pull-up calibration operation is inputted to the dummy reference impedance unit 120 and used to determine a total impedance value of the dummy reference impedance unit 120. Subsequently, a pull-down calibration operation is performed. In a similar manner to the pull-up calibration operation, the pull-down calibration operation is performed using the comparison unit 103 and the counter unit 105, so that a voltage of a second calibration node A becomes equal to the reference voltage VREF. Therefore, the total impedance value of the pull-down reference impedance unit 130 becomes equal to the impedance value of the dummy reference impedance unit 120. This operation is referred to as a pull-down calibration operation.
FIG. 2 is a block diagram of a conventional termination circuit.
The termination circuit refers to a circuit which receives the impedance codes PCODE<0:N> and NCODE<0:N) generated from the calibration circuit of FIG. 1 to terminate interface pads (e.g., input and output pads).
A pull-up termination unit 210 is designed to have a configuration similar to that of the pull-up reference impedance unit 110, and receives the pull-up impedance code PCODE<0:N>. Thus, the impedance value of the pull-up termination unit 210 tends to be similar to the impedance value of the pull-up reference impedance unit 110. That is, the impedance value of the pull-up termination unit 210 is the same as or proportional to the impedance value of the pull-up reference impedance unit 110. A pull-up termination enable signal PU_EN is a signal which turns on/off the pull-up termination unit 210. When the pull-up termination enable signal PU_EN is active, all resistors provided within the pull-up termination unit 210 are turned off (i.e., current does not flow through them). When the pull-up termination enable signal PU_EN is inactive, the resistors provided within the pull-up termination unit 210 are turned on or off according to the pull-up impedance code PCODE<0:N>.
A pull-down termination unit 220 is designed to have a configuration similar to that of the pull-down reference impedance unit 130, and receives the pull-down impedance code NCODE<0:N>. Thus, the impedance value of the pull-down termination unit 220 tends to be similar to the impedance value of the pull-down reference impedance unit 130. That is, the impedance value of the pull-down termination unit 220 is the same as or proportional to the impedance value of the pull-down reference impedance unit 130. A pull-down termination enable signal PD_EN is a signal which turns on/off the pull-down termination unit 220. When the pull-down termination enable signal PD_EN is inactive, all resistors provided within the pull-down termination unit 220 are turned off. When the pull-down termination enable signal PD_EN is active, the resistors provided within the pull-down termination unit 220 are turned on or off according to the pull-down impedance code NCODE<0:N>.
A pull-up voltage source resistor 201 symbolizes a total impedance value of a path coupled to an external voltage source which supplies a pull-up voltage, and a pull-down voltage source resistor 202 symbolizes a total impedance value of a path coupled to an external voltage source which supplies a pull-down voltage.
The above-described termination circuit may be a main driver of a data output driver which outputs data. When the pull-up termination enable signal PU_EN is inactive, the pull-up termination unit 210 sets the interface pad (e.g., a DQ pad) to a “high” voltage level. Thus, logic “high” data is outputted through the interface pad. When the pull-down termination enable signal PD_EN is active, the pull-down termination unit 220 sets the interface pad to a “low” voltage level. Thus, logic “low” data is outputted through the interface pad.
FIG. 3 is a block diagram of a conventional data output device.
Referring to FIG. 3, the data output device includes a calibration circuit 310, a termination circuit 320, and a selection signal generation unit 330. The calibration circuit 310 is the same as the circuit of FIG. 1, and the termination circuit 320 is the same as the circuit of FIG. 2.
In general, the pull-up and pull-down termination units 210 and 220 are laid out to have an impedance value of 240Ω each. However, a resistance of 120Ω is obtained by coupling the two termination units 210 and 220, each having the resistance of 240Ω, in parallel. Likewise, a resistance of 60Ω may be obtained by coupling four termination units 210 and 220, each having the resistance of 240Ω, in parallel. Therefore, the typical termination circuits having the resistances of 240Ω, 120Ω, and 60Ω includes seven total pull-up termination units 210 and pull-down termination units 220. As a larger number of the termination units 210 and 220 are driven, the influence of the voltage source resistors 201 and 202, described above with reference to FIG. 2, increases. Consequently, a mismatch occurs between a target impedance value and an actual impedance value, which is described in more detail below.
The selection signal generation unit 330 generates resistance selection information RES_CHO<0:A> which determines how many units of the seven termination units 210 and 220 are driven according to the target impedance value. In the DDR3 DRAM, one, two, and four termination units may be driven at a particular time to generate target impedances of 240 Ω, 120Ω, and 60Ω, respectively. There are two causes that increase the occurrence of a mismatch as the number of the driven termination units 210 and 220 increases.
First, as the target impedance value is lowered, the number of the driven termination units 210 and 220 increases. Since the magnitude of the power supply voltage VDDQ is constant and the target impedance value becomes lower, a current flowing through the voltage source resistors 201 and 202 increases. Since the impedance values of the voltage source resistors 201 and 202 are constant and the magnitude of the current flowing through the voltage source resistors 201 and 202 increases, the voltage drop caused by the voltage source resistors 201 and 202 increases. Accordingly, the drain-source voltages of a PMOS transistor and an NMOS transistor incorporated in the termination units 210 and 220 are lowered. Moreover, the drain-source voltage and the drain-source current of the PMOS and NMOS transistors are varied so that impedance values of the respective transistors increase. Hence, the total impedance value increases, causing a mismatch between the target impedance value and the actual impedance value.
Second, a mismatch occurs because the impedance values of the voltage source resistors 201 and 202 are constant, regardless of the number of the driven termination units 210 and 220. That is, when assuming that the number of the driven termination units 210 and 220 is N (where N is an integer and defined by 1≦N≦7), the total impedance value of the driven termination units 210 and 220 becomes 1/N due to the parallel connection because the impedance values of the voltage source resistors 201 and 202 do not change.
For example, it is assumed that the impedance values of the voltage source resistors 201 and 202 are 1Ω. Thus, where seven termination units 210 and 220 are all driven and each have an impedance of 240Ω, the original target impedance value is 34.29Ω (=240/7). The impedance values of the termination units 210 and 220 are determined by the impedance codes PCODE<0:N> and NCODE<0:N> generated from the reference impedance units 110, 120, and 130. Since the layouts of the reference impedance units 110, 120, and 130 are the same as those of the termination units 210 and 220, resistors similar to the voltage source resistors 201 and 202 exist in the reference impedance units 110, 120 and 130. Accordingly, the impedance codes PCODE<0:N> and NCODE<0:N> have code values which cause the respective termination units 210 and 220 to have impedance values of 239Ω. In this case, since the impedance values of the seven termination units 210 and 220 become 239Ω, the total impedance value becomes 35.14Ω (=239/7+1). Consequently, the actual impedance value becomes larger than the target value.
The difference between the resistance selection information RES_CHO<0:A> and the impedance codes PCODE<0:N> and NCODE<0:N> is as follows. The single termination units 210 and 220 each have an impedance value of 240Ω when the internal parallel resistors are all in an “on” state (i.e., the “on” state refers to when current flows through the resistor). Thus, the termination impedance value has the target impedance value. For example, the termination impedance value has the target impedance value of 120 Ω, 60Ω, and so on. When the target impedance value is 120Ω, two termination units 210 and 220 are enabled. When the target impedance value is 60Ω, four termination units 210 and 220 are enabled. The resistance selection information RES_CHO<0:N> is used to select the termination units 210 and 220 which should ideally be enabled to obtain the target impedance value.
On the other hand, the impedance codes PCODE<0:N> and NCODE<0:N> are generated in order to finely adjust the impedance value after the termination units 210 and 220 are enabled by the target impedance value. Even though an appropriate number of the termination units 210 and 220 are selected according to the target impedance value, the actual impedance value of the termination units 210 and 220 is changed according to the variation in the PVT conditions. That is, a mismatch occurs between the actual impedance value and the target impedance value. Since the performance of the termination circuit is greatly influenced by even a small change of the impedance value, it may be necessary to finely adjust the termination impedance value. To this end, a plurality of parallel resistors provided in the termination units 210 and 220 are turned on/off by the impedance codes PCODE<0:N> and NCODE<0:N> so that the termination impedance value coincides with the target impedance value even though the PVT conditions are varied. Through such procedures, the impedance values of the termination units 210 and 220 are finely adjusted.
That is, as a number of the termination units 210 and 220 that are driven increases, the actual impedance value of the termination units 210 and 220 becomes larger than the target impedance value.